About Me

I am currently employed as a Senior CAD Engineer at NVIDIA's Advanced Technology Group. Prior to this, I pursued my PhD at UCSD where I conducted research in the VLSI CAD Laboratory (ABKGroup) under the guidance of Professor Andrew B. Kahng. My research focused on digital VLSI physical design and Electronic Design Automation (EDA). Furthermore, I have also worked as a physical design engineer in Samsung's Design Technology team, where I was responsible for developing physical design methodologies for advanced technology nodes.

Education

University of California, San Diego (UCSD)

La Jolla, CA      September 2017 - June 2023

Ph.D., Electrical and Computer Engineering
Advisor: Prof. Andrew B. Kahng
Lab Website: https://vlsicad.ucsd.edu

Thesis: Robust Physical Design and Design Technology Co-Optimization Methodologies at Advanced VLSI Technology
Korea Advanced Institute of Science and Technology (KAIST)

Daejeon, Korea      February 2011 - February 2013

M.S., Electrical Engineering
Advisor: Prof. Chong-Min Kyung

Thesis: An Efficient Energy Management for Solar-Powered Wireless Visual Sensor Networks
Yonsei University

Seoul, Korea      March 2004 - February 2011

B.S., Electrical Engineering

**Academic leave for military service (The Republic of Korea Air Force) from 2006 to 2008


Technical Experiences

Senior CAD Engineer
Austin, TX      June 2022 - Present
Advanced Technology Group, NVIDIA Corp.

- Standard cell physical design -- Layout automation

Graduate Student Researcher
La Jolla, CA      September 2017 - June 2022
VLSI CAD Laboratory, UC San Diego (UCSD)

- Design-Technology Co-Optimization (DTCO) methodology for power, performance, area and cost (PPAC) evaluations at an early stage of technology development
- Machine Learning (ML)-assisted pathfinding for advanced technology nodes (Collaboration with Qualcomm)
- Technology-aware leakage optimization/placement methodology and power stapling for advanced technologies (Colloboration with Samsung)
- Optimization of top-level clock trees for memory-dominant designs (Collaboration with NXP semiconductors)
- Open-sourcing research project (OpenROAD, Open-source RTL-to-GDS) (https://theopenroadproject.org/) supported by Defense Advanced Research Projects Agency (DARPA)
- Collaboration with Qualcomm, Samsung, Intel, Arm, NXP and the C-DEN center (http://cden.ucsd.edu)
- Experienced with 7, 12, 14, 16, 28, 45, 65 and 130nm technologies from multiple academia/industry PDKs
- Teaching Assistant (TA) for VLSI Integrated Circuits and Systems Design (ECE260B/CSE241A, Lecturer: Prof. Andrew B. Kahng) in Winter 2019 (TA Evaluation)

Interim Engineering Intern
San Diego, CA      June 2021 - September 2021
Design Technology Team, Qualcomm Technologies, Inc.

- Routability assessment and IR Drop analysis using the PROBE2.0 framework (link) for 4nm node

Software Intern
Austin, TX      June 2020 - September 2020
Digital and Signoff Group, Cadence Design Systems

- Developed a buffering methodology for detailed balancing of clock trees in clock tree synthesis stage (ccopt, Innovus)

Physical Design Engineer
Hwaseong-si, Korea      February 2013 - July 2017
Design Technology Team, Foundry Business, Samsung Electronics

- Developed physical design methodology for Samsung 7/8/10/14/28nm technology nodes
- Developed reference flow scripts and routing technology files of Synopsys IC Complier and IC Compiler II for Samsung 10/14/28nm technology nodes
- Enabled complex design rule support in PnR tools for 10/14/28nm technology nodes
- Technical support for Samsung foundry customers (Qualcomm, NVIDIA, AMD, ST Microelectronics, etc.)
- Collaboration with EDA companies (Cadence, Synopsys and Mentor Graphics) for tool development at advanced technology nodes
- Experienced with multiple SoC projects for design verification (STA, DRC, LVS)
- Physical design and tape-out of the world-first Samsung 10nm SoC project

Graduate Student Researcher
Daejeon, Korea      February 2011 - February 2013
Smart Sensor Architecture Laboratory, KAIST

- Research for an energy management scheme of camera systems with solar-powered batteries in wireless visual sensor networks

Research

As a researcher, physical design area is in full of interesting and challenging problems, especially for the "next-generation" technologies. My research interests lie in technology-aware physical design methodology, design-technology co-optimization (DTCO), open-source EDA and machine learning-based prediction/optimization for physical design.

Technology-Aware Design Optimization

With the continuous evolution of technology, digital VLSI physical design faces numerous challenges that are both challenging and fascinating. These challenges include new device structures such as GAA and Nanosheet, the use of scaling boosters such as Backside PDN, buried power rails, and contact over active gate, large variations in terms of leakage, timing, power, complex and new design rules, and large signoff margins which necessitate new signoff methodologies to reduce the margins. In my current and past roles, I have been working on technology-aware design optimization methodologies, also known as manufacturing/process-aware design optimization. My research interests lie in a variety of areas, including technology-aware leakage/dynamic power reduction and performance improvement, IR-drop mitigation, routability evaluation, and enhancement at advanced technology nodes, particularly sub-3nm.

Design-Technology Co-Optimization (DTCO)

Design-Technology Co-Optimization (DTCO) goes beyond technology-aware design optimization. It involves ensuring that both technology and design considerations are well-defined and optimized for successful manufacturing, as well as achieving the best power, performance, area, and cost (PPAC) of chips. In the context of advanced nodes, DTCO has become increasingly important for foundry companies and chip designers alike to maximize their chip/technology competitiveness. In the early stages of technology development, there are numerous technology and design options to consider, such as evaluating the many combinations of standard-cell architectures alongside technology definitions.

Open-Source EDA

To be frank, academic research in the Electronic Design Automation (EDA) area has lost some of its momentum in recent times. This is largely due to the fact that most materials, Process Design Kits (PDK), design rule manuals, and cutting-edge intellectual properties (IP) are hidden under Non-Disclosure Agreements (NDA). Similarly, source codes from leading EDA companies are also kept under wraps. Consequently, academic researchers have limited access to outdated materials for their research. Recognizing this challenge, the OpenROAD project was launched in 2018 with the goal of developing complete and fully open-sourced tools that can autonomously implement 24-hour layout implementation (RTL to GDSII) with no human intervention. While the current tools provided by the OpenROAD project are not as good as those of leading EDA companies, they provide a strong foundation for academic research. The project includes shared databases, parsers for industry-standard formats, timing analysis, baseline codes for research, and more. I had the privilege of working on this project for over two years, and I am optimistic that it will help to spur academic physical design research by providing a more accessible platform for researchers.

Machine Learning in Physical Design

While I would not describe myself as a machine learning fanatic, I find the prospect of applying machine learning techniques to physical design challenges attractive as a researcher. Specifically, I am intrigued by areas such as floor planning, power planning (Power Delivery Network (PDN)), macro placement, routing, timing, and physical Engineering Change Order (ECO) where experienced human engineers are usually required. While commercial Electronic Design Automation (EDA) tools are quite capable, they still face challenges such as chicken-and-egg problems and heuristic approaches. As a result, there is still a long way to go to achieve the global optimum for physical design problems that offer the best tradeoffs between power, performance, area, and cost (PPAC). Machine learning can play a significant role in solving these challenges, and some recent works in the industry have shown promising perspectives and results. In my own research, I have explored the application of machine learning to PDN and Design-Technology Co-Optimization (DTCO), and I continue to follow interesting developments in machine learning and its potential applications in physical design.

Programming Language and EDA Tool

In my research and industry experience, I have written code in C++, Tcl, Perl, Skill and Python. Additionally, I am proficient in using version control software, Git and Perforce. Over my 10+ years of working in digital VLSI physical design and verification, I have used tools from multiple EDA companies. While working at Samsung as a physical design engineer, I was responsible for using Synopsys IC Compiler and IC Compiler II flows, and had some experience with Nitro-SoC of Mentor Graphics (now Siemens EDA). During my PhD, I primarily used Cadence Innovus and Synopsys IC Compiler II. I also have experience with Synopsys Design Compiler, Cadence Genus (Logic Synthesis), Synopsys Primetime, Cadence Tempus (Static Timing Analysis), Mentor CalibreDRC, Synopsys IC Validator (Signoff DRC), Ansys Redhawk, Cadence Voltus (EM/IR), and other tools. In addition to using commercial tools, I have also developed, maintained, and used various tools in the OpenROAD project, an open-source project for RTL to GDSII implementation.

Publications

The papers below have been made available in PDF format for easy access. Please be aware that all papers are copyrighted by the organization responsible for the corresponding conference or journal.
(**NOTE: All papers with Prof. Andrew B. Kahng have authors listed in alphabetical order.)


Journal

  • [J3] S. Choi, J. Jung, A. B. Kahng, Minsoo Kim, C.-H. Park, B. Pramanik and D. Yoon, "PROBE3.0: A Systematic Framework for Design-Technology Pathfinding with Improved Design Enablement", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 43(4) (2024), pp. 1218-1231.
    (Paper)

  • [J2] A. B. Kahng, Minsoo Kim, S. Kim and M. Woo, "RosettaStone: Connecting the Past, Present and Future of Physical Design Research", IEEE Design & Test 39(5) (2022), pp. 70-78.
    (Paper)

  • [J1] C.-K. Cheng, A. B. Kahng, H. Kim, Minsoo Kim, D. Lee, D. Park and M. Woo, "PROBE2.0: A Systematic Framework for Routability Assessment from Technology to Design in Advanced Nodes", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41(5) (2022), pp. 1495-1508.
    (Paper)


Conference

  • [C12] C.-T. Ho, A. Chandra, D. Guan, A. Ho, Minsoo Kim, Y. Li and H. Ren, "Novel Transformer Model Based Clustering Method for Standard Cell Design Automation", Proc. ACM International Symposium on Physical Design, 2024, pp. 195-203. (Best Paper Awards)
    (Paper)

  • [C11] C.-T. Ho, A. Ho, M. Fojtik, Minsoo Kim, S. Wei, Y. Li, B. Khailany and H. Ren, "NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model", Proc. ACM International Symposium on Physical Design, 2023, pp. 44-52.
    (Paper)

  • [C10] C.-K. Cheng, A. B. Kahng, I. Kang, Minsoo Kim, D. Lee, B. Lin, D. Park and M. Woo, "CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation", Proc. IEEE International Conference on Computer Design, 2021, pp. 366-373.
    (Paper) (Slides) (Video)

  • [C9] C. Chidambaram, A. B. Kahng, Minsoo Kim, G. Nallapati, S. C. Song and M. Woo, "A Novel Framework for DTCO: Fast and Automatic Routability Assessment with Machine Learning for Sub-3nm Technology Options", Proc. IEEE Symposium on VLSI Technology, 2021, pp. 1-2.
    (Paper) (Slides) (Video)

  • [C8] H. Fatemi, A. B. Kahng, Minsoo Kim and J. Pineda de Gyvez, "Optimal Bounded-Skew Steiner Trees to Minimize Maximum k-Active Dynamic Power", Proc. ACM/IEEE International Workshop on System-Level Interconnect Problems and Pathfinding, 2020, pp. 1-8.
    (Paper) (Slides)

  • [C7] A. Rovinski, T. Ajayi, Minsoo Kim, G. Wang and M. Saligane, "Bridging Academic Open-Source EDA to Real World Usability", Proc. ACM/IEEE International Conference on Computer-Aided Design, 2020, pp. 1-7.
    (Paper) (Slides) (Video)

  • [C6] V. A. Chhabria, A. B. Kahng, Minsoo Kim, U. Mallappa, S. S. Sapatnekar and B. Xu, "Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques", Proc. ACM/IEEE Asia and South Pacific Design Automation Conference, 2020, pp. 44-49.
    (Paper) (Slides)

  • [C5] T. Ajayi, V. A. Chhabria, M. Fogaça, S. Hashemi, A. Hosny, A. B. Kahng, Minsoo Kim, J. Lee, U. Mallappa, M. Neseem, G. Pradipta, S. Reda, M. Saligane, S. S. Sapatnekar, C. Sechen, M. Shalan, W. Swartz, L. Wang, Z. Wang, M. Woo and B. Xu, "Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project", Proc. ACM/IEEE Design Automation Conference, 2019, pp. 76:1-76:4.
    (Paper) (Slides)

  • [C4] T. Ajayi, D. Blaauw, T.-B. Chan, C.-K. Cheng, V. A. Chhabria, D. K. Choo, M. Coltella, S. Dobre, R. Dreslinski, M. Fogaça, S. Hashemi, A. Hosny, A. B. Kahng, Minsoo Kim, J. Li, Z. Liang, U. Mallappa, P. Penzes, G. Pradipta, S. Reda, A. Rovinski, K. Samadi, S. S. Sapatnekar, L. Saul, C. Sechen, V. Srinivas, W. Swartz, D. Sylvester, D. Urquhart, L. Wang, M. Woo and B. Xu, "OpenROAD: Toward a Self- Driving, Open-Source Digital Layout Implementation Tool Chain", Proc. Government Microcircuit Applications and Critical Technology Conference, 2019, pp. 1105-1110.
    (Paper) (Slides)

  • [C3] S. Heo, A. B. Kahng, Minsoo Kim, L. Wang and C. Yang, "Detailed Placement for IR Drop Mitigation by Power Staple Insertion in Sub-10nm VLSI", Proc. ACM/IEEE Design, Automation and Test in Europe, 2019, pp. 824-829.
    (Paper) (Slides)

  • [C2] S. Heo, A. B. Kahng, Minsoo Kim and L. Wang, "Diffusion Break-Aware Leakage Power Optimization and Detailed Placement in Sub-10nm VLSI", Proc. ACM/IEEE Asia and South Pacific Design Automation Conference, 2019, pp. 550-556. (nominated for Best Paper Awards)
    (Paper) (Slides)

  • [C1] Minsoo Kim, C.-M. Kyung and K. Yi, "An Energy Management Scheme for Solar-Powered Wireless Visual Sensor Networks Toward Uninterrupted Operations", Proc. IEEE International SoC Design Conference, 2013, pp. 23-26.
    (Paper)

Contact Me

E-mail Address
mik226 [at] ucsd [dot] edu


Work Address

NVIDIA Corporation
11001 Lakeline Blvd #100, Austin, TX 78717

Curriculum Vitae
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News

New Personal Website -- minsookim.me

My website has been renewed ! I have also enabled new domain, minsookim.me, for easy access. All materials are uploaded in my Github repository, which means it is open-sourced ! You can now access my website through mik226.github.io or minsookim.me.

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